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Table 7-21 · DMA Control Register 5C Hex (Continued)
Bit(s) Type
Description
Cycle Type
Sets the DMA transfer type and direction. These four bits directly set the PCI transfer type. Any of the sixteen PCI
commands may be used, but the recommended commands are as follows:
0010
0011
Data is moved from the PCI bus to the backend.
An I/O Read command is used on the PCI bus.
Data is moved from the backend to the PCI bus.
An I/O Write command is used on the PCI bus.
7:4
RW
0110
0111
1010
1011
1100
Data is moved from the PCI bus to the backend.
A Memory Read command is used on the PCI bus.
Data is moved from the backend to the PCI bus.
A Memory Write command is used on the PCI bus.
Data is moved from the PCI bus to the backend.
A Configuration Read command is used on the PCI bus.
Data is moved from the backend to the PCI bus.
A Configuration Write command is used on the PCI bus.
Data is moved from the PCI bus to the backend.
A Memory Read Multiple command is used on the PCI bus.
8
9
10
11
12
13
14
15
23:16
25:24
114
RW
RW
W
RO
RW
RW
RW
RW
RW
RO
DMA Enable
This bit must be set to 1 to enable any DMA transfers.
Transfer Width
Writing a '1' to this bit enables a 64-bit memory transaction. For 32-bit cores, this bit is read-only and is set to 0.
Flush Internal FIFOs
Only has an effect when the FIFO recovery logic is enabled. When written with a '1', all internal FIFOs will be
flushed. When the FIFOs are flushed, any data that was stored in them will be lost. Always returns 0 when read.
Reserved. Returns 0.
DMA Interrupt Status
A '1' in this bit indicates that the DMA cycle has completed and the interrupt is active. It is cleared by writing a '1' to
this bit. Set to 0 after reset.
DMA Interrupt Enable
Writing a '1' to this bit enables the DMA Complete interrupt. Set to 0 after reset.
Backend Interrupt Status
A '1' in this bit indicates an active backend interrupt condition (backend assertion of EXT_INTn). It is cleared by
writing a '1' to this bit. Set to 0 after reset. This bit can only be set when the backend interrupt is enabled (bit 15).
Backend Interrupt Enable
Writing a '1' to this bit enables the backend interrupt. Writing a '0' to this bit disables backend interrupt support.
Byte Enables
These eight bits directly set the byte enable values that will be used during the DMA transfer. When bit 16 is 0,
CBEN[0] will be active (LOW). Bit 17 controls CBEN[1], etc. In 32-bit cores, bits 23:20 are read-only and return 0.
For normal burst DMA transfers, these bits should be set to 0.
Reserved. Set to 0.
v4.0
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